? semiconductor components industries, llc, 2007 march, 2007 ? rev. 0 1 publication order number: 74hcu04/d 74hcu04 hex unbuffered inverter high ? performance silicon ? gate cmos the 74hcu04 is identical in pinout to the ls04 and the mc14069ub. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device consists of six single ? stage inverters. these inverters are well suited for use as oscillators, pulse shapers, and in many other applications requiring a high ? input impedance amplifier. for digital applications, the hc04 is recommended. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v; 2.5 to 6.0 v in oscillator configurations ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7.0 a requirements ? esd performance: hbm 2000 v; machine model 200 v ? chip complexity: 12 fets or 3 equivalent gates ? these are pb ? free devices http://onsemi.com marking diagrams hcu04 = specific device code a = assembly location l, wl = wafer lot y = year w, ww = work week g or = pb ? free package tssop ? 14 dt suffix case 948g 14 1 soic ? 14 d suffix case 751a 14 1 hcu04g awlyww 1 14 hcu 04 alyw 1 14 see detailed ordering and shipping information in the package dimensions sect ion on page 2 of this data sheet. ordering information (note: microdot may be in either location)
74hcu04 http://onsemi.com 2 logic diagram y1 a1 a2 a3 a4 a5 a6 y2 y3 y4 y5 y6 1 3 5 9 11 13 2 4 6 8 10 12 y = a pin 14 = v cc pin 7 = gnd function table inputs a l h outputs y h l pin assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 y5 a5 y6 a6 v cc y4 a4 y2 a2 y1 a1 gnd y3 a3 ordering information device package shipping ? 74HCU04DR2G soic ? 14 (pb ? free) 2500 / tape & reel 74hcu04dtr2g tssop ? 14* ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
74hcu04 http://onsemi.com 3 ??????????????????????? ??????????????????????? v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air soic package? tssop package? 500 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds soic or tssop package 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ?derating ? soic package: ?7mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time (figure 1) ? no limit ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
74hcu04 http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (voltages referenced to gnd) guaranteed limit symbol parameter test conditions v cc (v) ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = 0.5 v* |i out | 20 a 2.0 3.0 4.5 6.0 1.7 2.5 3.6 4.8 1.7 2.5 3.6 4.8 l.7 2.5 3.6 4.8 v v il maximum low ? level input voltage v out = v cc ? 0.5 v* |i out | 20 a 2.0 3.0 4.5 6.0 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 v v oh minimum high ? level output voltage v in = gnd |i out | 20 a 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 v v in = gnd |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.36 3.86 5.36 2.26 3.76 5.26 2.20 3.70 5.20 v ol maximum low ? level output voltage v in = v cc |i out | 20 a 2.0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 v v in = v cc |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.32 0.32 0.32 0.32 0.37 0.37 0.32 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 2.0 20 40 a 1. information on typical parametric values can be found in chapter 2 of the on semic onductor high ? speed cmos data book (dl129/d). 2. for v cc = 2.0 v, v out = 0.2 v or v cc ? 0.2 v. ????????????????????????????????? ????????????????????????????????? ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) guaranteed limit symbol parameter v cc (v) ? 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 1 and 2) 2.0 3.0 4.5 6.0 70 40 14 12 90 45 18 15 105 50 21 18 ns t tlh , t thl maximum output transition time, any output (figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance ? 10 10 10 pf 3. for propagation delays with loads other than 50 pf, see chapter 2 of the on semico nductor high ? speed cmos data book (dl129/d). 4. information on typical parametric values can be found in chapter 2 of the on semic onductor high ? speed cmos data book (dl129/d). c pd power dissipation capacitance (per inverter)* typical @ 25 c, v cc = 5.0 v pf 15 5. used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d).
74hcu04 http://onsemi.com 5 figure 1. switching waveforms t r v cc gnd 90% 50% 10% 90% 50% 10% input a output y t phl t plh t thl t tlh *includes all probe and jig capacitance figure 2. test circuit c l * test point device under test output figure 3. logic detail (1/6 of device shown) t f a v cc y typical applications figure 4. crystal oscillator figure 5. stable rc oscillator figure 6. schmitt trigger figure 7. high input impedance single ? stage amplifier with a 2 to 6 v supply range r 2 1/6 hcu04a c 1 r 2 > > r 1 c 1 < c 2 v out c 2 r 1 r 2 r 1 c 1/6 hcu04a 1/6 hcu04a 1/6 hcu04a v out r 2 r 1 v in v out 1/6 hcu04a 1/6 hcu04a r 2 > 6r 1 v cc input output 1 m 1 m 1/6 hcu04a
74hcu04 http://onsemi.com 6 figure 8. multi ? stage amplifier figure 9. led driver for reduced power supply current, use high ? efficiency leds such as the hewlett ? packard hlmp series or equivalent. v cc input output 1/6 hcu04a 1/6 hcu04a 1/6 hcu04a +v 1/6 hcu04a typical applications
74hcu04 http://onsemi.com 7 package dimensions soic ? 14 case 751a ? 03 issue h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint* 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
74hcu04 http://onsemi.com 8 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
74hcu04 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 74hcu04/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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